1. Field of the Invention
The present invention relates to a semiconductor structure having an interconnect structure which includes a plurality of conductive traces. More specifically, invention relates a structure and method for maximizing the volume of a low dielectric constant material which is located between adjacent interconnect traces.
2. Description of the Prior Art
In the era of deep sub-micron semiconductor fabrication, the need to minimize interconnect capacitance is becoming more important to overcome the increased RC delay which results from shrinking geometry. One method of minimizing the capacitance of the interconnect structure of a semiconductor device is to provide a dielectric material having a low dielectric constant (K) between the conductive traces of the interconnect structure, such that intra-trace capacitance (which typically dominates the capacitance of the interconnect structure) is minimized. It would therefore be desirable to have a semiconductor structure which maximizes the volume of low dielectric constant material located between adjacent conductive traces in an interconnect structure.
U.S. Pat. No. 5,482,900 discloses the semiconductor structures illustrated in FIGS. 1-3. FIG. 1 is a cross sectional view of a semiconductor structure 1 including a metallurgy pattern 10, an insulating layer 11 and a semiconductor substrate 12. The metallurgy pattern 10 is covered with a thin conformal layer 14. A non-conformal layer 16 of spin-on-glass (SOG) 16 is deposited over layer 14. The narrow spacing between the lines of metallurgy pattern 10 can result in voids, such as void 18, between these lines. These voids exist because the spaces between the lines are so small that these spaces cannot be filled with the SOG material. As illustrated in FIG. 2, the SOG layer 16 is etched back to the upper surface of layer 14 where layer 14 extends over the metallurgy pattern 10. An oxide layer 20 is then formed over the resulting structure.
FIG. 3 is a cross sectional view of another semiconductor structure 2 disclosed in U.S. Pat. No. 5,482,900. Semiconductor structure 2 includes semiconductor substrate 12, insulating layer 11, metallurgy pattern 13, oxide layer 22, conformal oxide layer 22, SOG layer 28 and insulating layer 30. Semiconductor structure 2 is similar to semiconductor structure 1 (FIGS. 1-2), but additionally includes oxide layer 22 formed over metallurgy pattern 13.
As previously discussed, it would be desirable to have a semiconductor structure which maximizes the volume of a low dielectric constant material between conductive traces in an interconnect structure.